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Add nucleo-u5a5zj-q
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‎templates/blinky/nucleo-u5a5zj-q/Makefile

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CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion -Wformat-truncation -fno-common
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections -Wno-shadow
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CFLAGS += -I. -Iinclude -Icmsis_core/CMSIS/Core/Include -Icmsis_u5/Include
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CFLAGS += -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = main.c syscalls.c
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SOURCES += cmsis_u5/Source/Templates/gcc/startup_stm32u5a5xx.s
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ifeq ($(OS),Windows_NT)
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RM = cmd /C del /Q /F
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else
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RM = rm -rf
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endif
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build: firmware.bin
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firmware.elf: cmsis_core cmsis_u5 hal.h link.ld Makefile $(SOURCES)
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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flash: firmware.bin
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STM32_Programmer_CLI -c port=swd -e all -w $< 0x8000000 -hardRst
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# st-flash --reset write $< 0x8000000
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cmsis_core:
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git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_u5:
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git clone -q -c advice.detachedHead=false --depth 1 -b v1.4.1 https://github.com/STMicroelectronics/cmsis_device_u5 $@
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clean:
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$(RM) firmware.* cmsis_*

‎templates/blinky/nucleo-u5a5zj-q/hal.h

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// Copyright (c) 2025 Cesanta Software Limited
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// https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf
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// SPDX-License-Identifier: MIT
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#pragma once
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#include <stm32u5a5xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define CLRSET(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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// System clock
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enum { AHB_DIV = 1, APB1_DIV = 1, APB2_DIV = 1 };
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enum { PLL_HSI = 16, PLL_M = 1, PLL_N = 10, PLL_R = 2 }; // 80 Mhz
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// #define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_R) * 1000000)
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#define SYS_FREQUENCY 16000000
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#define APB2_FREQUENCY (SYS_FREQUENCY / APB2_DIV)
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#define APB1_FREQUENCY (SYS_FREQUENCY / APB1_DIV)
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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static inline GPIO_TypeDef *gpio_bank(uint16_t pin) {
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switch (PINBANK(pin)) {
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case 0: return GPIOA;
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case 1: return GPIOB;
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case 2: return GPIOC;
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case 3: return GPIOD;
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case 4: return GPIOE;
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case 5: return GPIOF;
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case 6: return GPIOG;
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case 7: return GPIOH;
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case 8: return GPIOI;
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case 9: return GPIOJ;
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default: return NULL;
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}
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}
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB2ENR1 |= BIT(PINBANK(pin)); // Enable GPIO clock
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CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline bool uart_init(USART_TypeDef *uart, unsigned long baud) {
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// https://www.st.com/resource/en/datasheet/stm32u5a5aj.pdf
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
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if (uart == USART1) {
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freq = APB2_FREQUENCY, RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
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tx = PIN('A', 9), rx = PIN('A', 10);
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} else if (uart == USART2) {
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freq = APB1_FREQUENCY, RCC->APB1ENR1 |= RCC_APB1ENR1_USART2EN;
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tx = PIN('A', 2), rx = PIN('A', 3);
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} else if (uart == USART2) {
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freq = APB1_FREQUENCY, RCC->APB1ENR1 |= RCC_APB1ENR1_USART3EN;
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tx = PIN('B', 10), rx = PIN('B', 11);
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} else {
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return false;
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}
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable this UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 |= BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
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return true;
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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static inline void rng_init(void) {
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RCC->AHB2ENR1 |= RCC_AHB2ENR1_RNGEN;
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RNG->CR |= RNG_CR_RNGEN;
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}
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static inline uint32_t rng_read(void) {
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while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
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return RNG->DR;
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}
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#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 41.1
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// Helper macro for MAC generation
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{2, \
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UUID[0] ^ UUID[1], \
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UUID[2] ^ UUID[3], \
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UUID[4] ^ UUID[5], \
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UUID[6] ^ UUID[7] ^ UUID[8], \
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UUID[9] ^ UUID[10] ^ UUID[11]}
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// t: expiration time, prd: period, now: current time. Return true if expired
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static inline bool timer_expired(volatile uint64_t *t, uint64_t prd,
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uint64_t now) {
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if (now + prd < *t) *t = 0; // Time wrapped? Reset timer
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if (*t == 0) *t = now + prd; // Firt poll? Set expiration
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if (*t > now) return false; // Not expired yet, return
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*t = (now - *t) > prd ? now + prd : *t + prd; // Next expiration time
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return true; // Expired, return true
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}
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// Fill in stack with markers, in order to calculate stack usage later
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extern unsigned char _estack, _end;
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static inline void stack_fill(void) {
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uint32_t dummy, *p = (uint32_t *) &_end;
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while (p < &dummy) *p++ = 0xa5a5a5a5;
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}
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static inline long stack_usage(void) {
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uint32_t *sp = (uint32_t *) &_estack, *end = (uint32_t *) &_end, *p = sp - 1;
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while (p > end && *p != 0xa5a5a5a5) p--;
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return (sp - p) * sizeof(*p);
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}
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static inline void clock_init(void) {
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SCB->CPACR |= 15 << 20; // Enable FPU
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FLASH->ACR |= FLASH_ACR_LATENCY_4WS;
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// FLASH->ACR |= FLASH_ACR_LATENCY_4WS | FLASH_ACR_ICEN | FLASH_ACR_DCEN;
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#if 0
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#if 0
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CLRSET(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos);
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CLRSET(RCC->PLLCFGR, RCC_PLLCFGR_PLLN, PLL_N << RCC_PLLCFGR_PLLN_Pos);
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CLRSET(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLCFGR_PLLSRC_HSI);
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN;
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#else
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RCC->PLLCFGR = BIT(24) | BIT(20) | (PLL_N << 8) | RCC_PLLCFGR_PLLSRC_HSI |
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(7 << 27) | BIT(16);
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RCC->CR |= RCC_CR_PLLON;
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#endif
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while (!(RCC->CR & RCC_CR_PLLRDY)) spin(1);
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#if 0
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CLRSET(RCC->CFGR, RCC_CFGR_PPRE1, (3 + APB1_DIV / 2) << RCC_CFGR_PPRE1_Pos);
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CLRSET(RCC->CFGR, RCC_CFGR_PPRE2, (3 + APB2_DIV / 2) << RCC_CFGR_PPRE1_Pos);
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#endif
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) spin(1);
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#else
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY)) spin(1);
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RCC->CFGR1 &= ~(RCC_CFGR1_SW);
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RCC->CFGR1 |= (RCC_CFGR1_SW_0);
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while ((RCC->CFGR1 & RCC_CFGR1_SWS) != RCC_CFGR1_SWS_0) spin(1);
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#endif
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rng_init(); // Initialise random number generator
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RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; // Enable SYSCFG
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SystemCoreClock = SYS_FREQUENCY; // Required by CMSIS
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SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
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}

‎templates/blinky/nucleo-u5a5zj-q/link.ld

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ENTRY(Reset_Handler);
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MEMORY {
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flash(rx) : ORIGIN = 0x08000000, LENGTH = 256k
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sram(rwx) : ORIGIN = 0x20000000, LENGTH = 64k
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}
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_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
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_eflash = ORIGIN(flash) + LENGTH(flash); /* points to end of flash */
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SECTIONS {
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.vectors : { KEEP(*(.isr_vector)) } > flash
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.text : { *(.text* .text.*) } > flash
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.rodata : { *(.rodata*) } > flash
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.data : { _sdata = .; *(.first_data) *(.data SORT(.data.*)) _edata = .; } > sram AT > flash
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_sidata = LOADADDR(.data);
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.bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > sram
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. = ALIGN(8);
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_end = .;
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}

‎templates/blinky/nucleo-u5a5zj-q/main.c

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// Copyright (c) 2025 Cesanta Software Limited
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// SPDX-License-Identifier: MIT
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#include "hal.h"
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#define UART_DEBUG USART1
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#define LED1_PIN PIN('C', 7) // Green
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#define LED2_PIN PIN('B', 7) // Blue
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#define LED3_PIN PIN('G', 2) // Red
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#define BLINK_PERIOD_MS 500 // LED blinking period in millis
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#define LOG_PERIOD_MS 1000 // Info log period in millis
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static uint16_t s_pins[] = {LED1_PIN, LED2_PIN, LED3_PIN};
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//static uint16_t s_pins[] = {LED1_PIN, PIN('A', 3)};
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#define NUM_LEDS (sizeof(s_pins) / sizeof(s_pins[0]))
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int _write(int fd, char *ptr, int len) {
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if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
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return len;
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}
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uint32_t SystemCoreClock; // Required by CMSIS. Holds system core cock value
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void SystemInit(void) { // Called automatically by startup code
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clock_init(); // Sets SystemCoreClock
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}
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static volatile uint64_t s_ticks; // Milliseconds since boot
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void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
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}
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static void led_task(void) { // Blink LED every BLINK_PERIOD_MS
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static uint64_t timer = 0;
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static size_t idx;
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if (timer_expired(&timer, BLINK_PERIOD_MS, s_ticks)) {
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for (size_t i = 0; i < NUM_LEDS; i++) gpio_write(s_pins[i], false);
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gpio_write(s_pins[idx], true);
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if (++idx >= NUM_LEDS) idx = 0;
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}
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}
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static void log_task(void) { // Print a log every LOG_PERIOD_MS
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static uint64_t timer = 0;
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if (timer_expired(&timer, LOG_PERIOD_MS, s_ticks)) {
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printf("tick: %5lu, CPU %lu MHz\n", (unsigned long) s_ticks,
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(unsigned long) (SystemCoreClock / 1000000));
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for (size_t i = 0; i < 8; i++) {
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printf("%#lx\n", gpio_bank(i)->LCKR);
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}
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}
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}
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int main(void) {
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for (size_t i = 0; i < NUM_LEDS; i++) gpio_output(s_pins[i]);
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uart_init(UART_DEBUG, 115200);
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for (;;) {
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led_task();
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log_task();
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}
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return 0;
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}

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