Integrate rv32i conformance tests

.gitignore

@@ -1,2 +1,8 @@
 emu-rv32i
 test1
+sig.txt
+rom.v
+debug.txt
+# ignore generated files
+*.mem
+*.signature.output

CSRs.h

@@ -0,0 +1,93 @@
+/* Modified by Nober <s0913768710@gmail.com>
+    13-DEC-2019 - Define all CSR macro
+*/
+
+/*
+RISCV emulator for the RV32I architecture
+based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/
+stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the
+compliance test by Frank Buss, 2018
+
+Requires libelf-dev:
+
+sudo apt-get install libelf-dev
+
+
+Compile it like this:
+
+gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i
+
+
+It is compatible to Spike for the command line arguments, which means you can
+run the compliance test from https://github.com/riscv/riscv-compliance like
+this:
+
+make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator
+variant
+
+It is also compatible with qemu32, as it is used for Zephyr. You can compile the
+Zephyr examples for qemu like this:
+
+cd zephyr
+source zephyr-env.sh
+cd samples/synchronization
+mkdir build && cd build
+cmake -GNinja -DBOARD=qemu_riscv32 ..
+ninja
+
+After this you can run it with the emulator like this:
+
+emu-rv32i zephyr/zephyr.elf
+
+
+original copyright:
+*/
+
+
+
+/*
+ * RISCV emulator
+ *
+ * Copyright (c) 2016 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+
+
+// ====================================================== //
+// =================== User Trap Setup ================== //
+// ====================================================== //
+uint32_t ustatus; /* User status register  */
+uint32_t uie;     /* User interrupt-enable register */
+uint32_t utvec;   /* User trap handler base address */
+// ====================================================== //
+// ================= User Trap Handling ================= //
+// ====================================================== //
+uint32_t uscratch; /* Scratch register for user trap handlers*/
+uint32_t uepc;     /* User exception program counter */
+uint32_t ucause;   /* User trap cause*/
+uint32_t ubadaddr; /* User bad address */
+uint32_t uip;      /* User interrupt pending */
+// ====================================================== //
+// ============== User Floating-Point CSRs ============== //
+// ====================================================== //
+uint32_t fflags; /* Floating-Point Accrued Exceptions*/
+uint32_t frm;    /* Floating-Point Dynamic Rounding Mode*/

Makefile

@@ -1,4 +1,30 @@
 BINS = emu-rv32i test1
+TEST_TARGETS = \
+	C-ADD.elf \
+	C-ADDI.elf \
+	C-ADDI4SPN.elf \
+	C-AND.elf \
+	C-ANDI.elf \
+	C-BEQZ.elf \
+	C-BNEZ.elf \
+	C-J.elf \
+	C-JAL.elf \
+	C-JALR.elf \
+	C-JR.elf \
+	C-LI.elf \
+	C-LUI.elf \
+	C-LW.elf \
+	C-LWSP.elf \
+	C-MV.elf \
+	C-NOP.elf \
+	C-OR.elf \
+	C-SLLI.elf \
+	C-SRAI.elf \
+	C-SRLI.elf \
+	C-SUB.elf \
+	C-SW.elf \
+	C-SWSP.elf \
+	C-XOR.elf
 
 CROSS_COMPILE = riscv-none-embed-
 RV32I_CFLAGS = -march=rv32i -mabi=ilp32 -O3 -nostdlib
@@ -7,7 +33,6 @@ CFLAGS = -O3 -Wall
 LDFLAGS = -lelf
 
 all: $(BINS)
-
 emu-rv32i: emu-rv32i.c
 	$(CC) $(CFLAGS) -o $@ $< $(LDFLAGS)
 

README.md

@@ -12,23 +12,33 @@ How to compile it:
 ```shell
 $ gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i
 ```
+or
+```shell
+$ make emu-rv32i
+```
 
-Run RV32I compliance tests.
-Assume `emu-rv32i` in `$PATH` environment variable.
+Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance
+- Must install the [risc-v toolchain](https://xpack.github.io/riscv-none-embed-gcc/)
 ```shell
 $ git clone https://github.com/riscv/riscv-compliance
-$ cd riscv-compliance
+$ cd rv32emu
+$ cp rv32emu ../riscv-compliance/riscv-target
+$ cd ../riscv-compliance
 $ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=emu-rv32i variant
 ```
-
-Compiling and running simple code:
+- Run RV32IMC compliance tests.
+Assume `emu-rv32i` in `$PATH` environment variable.
 ```shell
-$ riscv32-unknown-elf-gcc -O3 -nostdlib test1.c -o test1
+$ git clone https://github.com/riscv/riscv-compliance
+$ cd rv32emu
+$ cp rv32emu ../riscv-compliance/riscv-target # If having copied the makefile.include to riscv-compliance, it can be ignored.
+$ cd riscv-compliance
+$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=/abs/path/to/emu-rv32i variant
 ```
 
-or
+Compiling and running simple code:
 ```shell
-$ riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -O3 -nostdlib test1.c -o test1
+$ make test1
 ```
 
 then
@@ -37,8 +47,17 @@ $ ./emu-rv32i test1
 Hello RISC-V!
 ```
 
-RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`.
+- RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`.
+
+
+Passed RV32C compliance tests from https://github.com/riscv/riscv-compliance
+```shell
+make C-ADDI.log
+```
+If there is no accident, it will output the `TEST PASSED`
+
 
+- RV32C instructions can be enabled by commenting `#define RV32C`
 ## How to build RISC-V toolchain from scratch
 
 https://github.com/riscv/riscv-gnu-toolchain